This invention relates generally to a system and method for maintaining two or more clocks in pseudo-synchronization, and more specifically to a system and method using cross coupled phase lock loop circuits to maintain clocks in pseudo-synchronization, the system and method being especially applicable to fault-tolerant applications. The invention further relates to a system and method for maintaining the pseudo-synchronized clocks synchronized to a system clock.
Phase lock loop (PLL) circuits are devices that allow one clock (the slave clock) to lock onto or follow another clock (the master clock) in frequency and in phase. PLL circuits are often used in fault-tolerant systems that require redundancy. Redundant channels are provided, for example, in aircraft navigation and control systems to ensure that these systems remain operative even if a fault occurs in one of the channels. Upon the occurrence of a fault in one channel, the system employs the other channel to remain operative. The use of the master/slave concept provides a clock signal having the same frequency and phase relationship for each of the channels so that communication between the channels can be maintained.
There are a number of problems associated with the conventional master/slave PLL concept. In order to achieve complete redundancy, as is often required in fault-tolerant applications, it is desirable to have fully independent channels. With fully independent channels, each channel is provided with and runs on its own separate oscillator. In the conventional PLL structure, however, only a single oscillator is used and multiple clock signals are generated and synchronized to that single oscillator. Such a system results in lack of total redundancy because of serial operations based on the single oscillator. If the single oscillator fails, for example, the redundancy is inoperative. Additionally, in a conventional master/slave clock arrangement, the slave PLL must be able to either advance the phase or retard the phase in response to the performance of the master PLL. This can result in an instantaneous clock signal frequency greater than the nominal clock signal frequency. All devices utilizing the clock signal must therefore be over designed for this higher frequency and such over design can result in increased cost and complexity.
In the prior art, if two independent oscillators were employed to generate two independent clock signals to achieve total redundancy and PLLs were used to synchronize the two clock signals, such prior solutions resulted in instability of the system. For example, if the phase of the clock signal used by a first channel A was detected to be advanced by 90xc2x0 relative to the phase of the clock signal used by a second channel B, the PLL for channel A might attempt to retard the phase of its clock signal by 90xc2x0 to align with the clock signal of channel B. Simultaneously the channel B PLL might attempt to advance the phase of its clock signal by 90xc2x0 to align with the clock signal of channel A. The result after both corrections are made would be a relative phase of xe2x88x9290xc2x0. The process then repeats itself in reverse. The loop thus becomes unstable.
Thus, a need exists for a system and method to achieve pseudo-synchronization between two or more totally independent clock signals that overcomes the deficiencies of prior solutions.
In accordance with one embodiment of the invention, two PLL circuits, each associated with an independent channel, are cross coupled. Each channel also includes an independent oscillator, each providing a clock signal having a nominal frequency nf. Each PLL operates by dividing the input clock signal to generate an output clock signal having a nominal frequency f. Phase information is exchanged between the two PLLs at a frequency (1/m) f. A phase detector measures the relative phase relationship between the two exchanged clock signals and then adjusts the phase of the PLL output if the phase difference exceeds a predetermined value. If the phase difference exceeds the predetermined value, the phase of the leading clock signal is retarded by temporarily increasing the divide ratio of the PLL providing the advanced phase clock signal.